The present invention relates to an MPEG video decoder for decoding a bit-stream which has been encoded according to a Moving Picture Expert Group (hereinafter, referred to as an MPEG) standard, and an MPEG video decoding method.
The MPEG standard has been heretofore employed as an international standard for a bit rate reduction of picture data. A moving picture encoding technology and a moving picture decoding technology, which are in conformity with the MPEG standard, are inevitable for recent multi-media environments. Many moving picture encoding apparatus and moving picture decoding apparatus which adopt the MPEG standard have been developed.
A bit rate reduction encoding by the MPEG standard includes a constant bit rate encoding (hereinafter, referred to as a CBR encoding) in which a data rate after encoding is substantially constant and a variable bit rate encoding (hereinafter, referred to as a VBR encoding) in which the data rate after encoding is not constant.
The CBR encoding is used when a transmission line is, in a STM mode (Synchronous Transfer Mode). The VBR encoding is used when the transmission line in an ATM mode (Asynchronous Transfer Mode), as well as when the transmission line is storage media such as a DVD (Digital Video Disc).
Descriptions for a picture type, a bit-stream, a MPEG video encoder and a MPEG video decoder, which are used in the MPEG standard, will be made below.
(1) Picture Type
In the MPEG standard, used are three types of pictures for a high efficiency encoding, which are called an intra coded picture (hereinafter, referred to as an I picture), a predictive coded picture (hereinafter, referred to as a P picture) and a bi-directional predictive coded picture (hereinafter, referred to as a B picture), respectively.
The I picture does not use information relating to other pictures, and encoded by only information relating to itself. The P picture is encoded by using the I picture or the P picture in the past as a reference picture. The B picture is encoded using the I picture or the P picture in the past and future.
Although the I picture exhibits a low compression rate, the I picture can be encoded independently from other pictures, so that the I picture is utilized as an access point in random accessing. For decoding the I picture, information relating to other pictures is unnecessary. Although the P picture exhibits a compression rate higher than that of the I picture, the P picture requires information relating to the I picture in the past for its decoding. Moreover, although the B picture exhibits the highest compression rate in all of the pictures, the B picture needs the information relating to the I or P picture for its decoding.
(2) Bit-Stream
FIG. 1 is a schematic view showing a structure of the bit-stream adopting the MPEG standard. The bit-stream consists of a sequence header 31, a GOP header (a group of picture header) 32, a picture header 33, picture data 34 and a sequence end code 35. The bit-stream includes a sequence extension and extension and user data in addition to these components. Illustrations and descriptions for them are omitted here.
The sequence header 31 always exists at the initial portion of the bit-stream. In the sequence header 31, included are a horizontal size value, a vertical size value and a parameter showing an aspect ratio information.
The GOP header 32 is added to the bit-stream when many pictures are managed for each GOP. The GOP consists of a plural types of pictures, and the first picture of the GOP is always the I picture. The GOP is inevitable in a MPEG 1 (Moving Picture Experts Group Phase 1), and optional in a MPEG 2 (Moving Picture Experts Group Phase 2).
The picture head 33 indicates the beginning of decoded data for one picture. A parameter (a temporal reference) indicating the order of the pictures and a picture type are included in the picture head 33.
The picture data 34 is encoded one for one picture. The picture data 34 is followed by the GOP header 32, the subsequent picture head 33 or the sequence end code 35. The sequence end code 35 indicates the end of the bit-stream.
(3) Structure of MPEG Video Encoder
FIG. 2 is a block diagram showing a MPEG video encoder.
The MPEG video encoder consists of a picture rearrangement section 41, a motion estimation section 42, an adder 43, a discrete cosine transform (hereinafter, referred to as a DCT) section 44, a quantization section 45, a variable length code section 46, a multiplexer section 47, a buffer 48, an inverse quantization section 49, an inverse discrete cosine transform (hereinafter, referred to as an IDCT) section 50, an adder 51, a picture storage section 52 and a motion prediction section 53.
Since the B picture decoded by referring to the pictures in the past and future exists in the MPEG, it is necessary to process the picture in the future prior to the picture in the past. The picture rearrangement section 41 rearranges the pictures in the processing order.
The motion estimation section 42 receives the picture from the picture rearrangement section 41, and outputs various kinds of parameters required in decoding, such as a picture type, a presentation time stamp (PTS), a quantization step size, a motion vector and an encoded mode. These parameters are supplied to the motion prediction section 53, and added also to the bit-stream in the multiplexer section 47.
The adder 43 calculates the differential between the picture outputted from the motion estimation section 42 and the reference picture outputted from the motion prediction section 53. Since the reference picture is not outputted from the motion prediction section 53 at the time when the I picture is processed, the picture outputted from the motion estimation section 42 is inputted to the DCT section 44 via the adder 43. Moreover, when either the P picture or the B picture is processed, the adder 43 calculates the differential between the picture outputted from the motion estimation section 42 and the reference picture outputted from the motion prediction section 53, and outputs the differential to the DCT section 44.
The DCT section 44 performs a discrete cosine transform for the data supplied from the adder 43, divides the data into each of frequency components, and removes high frequency components, thus reducing the quantity of the data. The quantization section 45 removes information with less importance by the quantization that is a non-reversible step. The variable length code section 46 zigzag-scans the quantized data so as to perform a variable encoding for the quantized data, thus further reducing the quantity of data.
On the other hand, the inverse qunatization section 49 and the IDCT section 50 performs an inverse discrete cosine transform and an inverse quantization for the data that has been subjected to the discrete cosine transform by the DCT section 44 and the quantization by the quantization section 45. The adder 51 adds the data outputted from the IDCT section to the reference picture outputted from the motion prediction section 53 so as to restore the picture, thus storing the restored picture in the picture storing section 52. The motion prediction section 53 performs a motion prediction based on the motion vector outputted from the motion estimation section 42, the output from the adder 51, and the picture stored in the picture storing section 52. Furthermore, the motion prediction section 53 creates a reference picture from either the output of the adder 51 or the picture stored in the picture storing section 52, and outputs the reference picture to the adder 43.
The multiplexer section 47 multiplexes the data outputted from the variable length code section 46 and the parameters such as the encoded mode and the motion vector outputted from the motion estimation section 42, thus creating the bit-stream. The buffer 48 temporarily stores the bit-stream created.
(4) Structure of MPEG Video Decoder (No. 1)
FIG. 3 exemplifies a block diagram of a MPEG video decoder.
The MPEG video decoder shown in FIG. 3 consists of a bit-stream input terminal 60, a bit-stream buffer 61, a picture decoding section 62, a decoding frame buffer 63, a decoding switch 64 and a picture data output section 65. Furthermore, the picture data output section 65 consists of a display control section 65a, a display switch 65b and a display buffer 65c. 
The bit-stream buffer 61 stores the bit-stream inputted from the input terminal 60, and sequentially outputs the bit-stream to the picture decoding section 62. Upon receipt of the vertical synchronous signal V-Sync 71 from the display control section 65a, the decoding switch 64 outputs the decoding start command 72 to the picture decoding section 62. Upon receipt of the decoding start command 72 from the decoding switch 64, the picture decoding section 62 receives the bit-stream for one picture from the bit-stream buffer 61, so as to perform a variable length decoding processing, an inverse quantization processing, an inverse discrete cosine transform processing and a motion prediction. The picture decoded by the picture decoding section 62 in the above described manner is sequentially stored in the decoding frame buffer 63. It should be noted that when the picture decoding section 62 decodes the bit-stream, the picture decoding section 62 refers to the picture previously stored in the decoding frame buffer 63 according to demand. Accordingly, the decoding frame buffer 63 has to keep the decoded picture stored therein until the decoded picture is not referred to for decoding other pictures. Moreover, when the bit-stream is decoded, the picture decoding section 62 extracts the display time stamp (PTS) 76 from the bit-stream, thus outputting the PTS 76 to the picture data output section 65.
The display control section 65a compares its system time clock (STC) with the display time stamp PTS 76 of the decoded picture, and if both are coincident with each other, the display control section 65a outputs the transfer command 73 to the display switch 65b. Upon receipt of the transfer command 73, the display switch 65b transfers data for one picture (picture data) from the decoding frame buffer 63 to the display buffer 65c. The picture data stored in the display buffer 65c is transmitted to the display unit 66 from the display control section 65a in synchronization with the vertical synchronous signal V-Sync 71.
In the above described manner, the conventional MPEG video decoder, the bit-stream reads out one picture by one picture from the bit-stream buffer 61 at a timing synchronous with the vertical synchronous signal V-Sync 71, and performs a decoding processing for the read-out bit-stream. At the same time, the conventional MPEG video decoder transmits the picture from the display buffer 65c to the display unit 66 at the timing in synchronization with the vertical synchronous signal V-Sync 71. Thus, the picture displayed on the display unit 66 is updated at the timing in synchronization with the vertical synchronous signal V-Sync 71, and the moving picture is displayed on the display unit 66.
Hereupon, it is required for the MPEG video decoder to decode the bit-stream in real time, in order to obtain a smooth reproduced moving picture. To satisfy this requirement, the MPEG video decoder has to possess an ability to completely decode the bit-stream for one picture within one frame time (a reciprocal of the number of frames per second) and to output data for one picture per one frame time to the display unit. The conventional MPEG video decoder shall terminates the decoding of the bit-stream for one picture within one frame time. The timing when the MPEG video decoder starts to decode the bit-stream for one picture and the timing when the MPEG video decoder outputs data for one picture to the display unit therefrom are made to be synchronous with the vertical synchronous signal V-Sync.
(Other Prior Arts)
In the MPEG, when a video with a frame rate of 24 frames/sec in a moving picture is converted to a video for use in TVs with a frame rate of 30 frames/sec, i.e., a telecine conversion, conversion processes called a 3-2 pull down are performed. In the 3-2 pull down, a command called a repeat first field is used. The repeat first field command is the one indicating “Display the initially displayed field once more”.
FIG. 4 is a figure schematically showing the telecine conversion by the 3-2 pull down. In FIG. 4, the symbol * represents the repetition of the image, similarly. The symbol *′ represents the repetition of the same image by the repeat first field.
One frame of a television video displayed by a NTSC (National Television System Committee) scheme is divided into two fields, i.e., a top field and a bottom field. Accordingly, a TV video for one second consists of am image for 60 fields.
As shown in FIG. 4, in the case where the video of the moving picture is converted to the TV video, one picture is allocated to the top field (T) and bottom field (B) of each frame, whereby the picture data for 24 frames is created. However, if the picture data for 24 frames is displayed as it is, a shortage of the picture data amounting to 6 frames (12 fields) is brought about. To cope with such situation, in the telecine conversion, the repeat first field command is added to 12 frames among 24 frames, and the picture data for 12 fields is created. To be specific, by adding the repeat first field command to, for example, an odd-numbered frame, the picture of the odd-numbered frame will be displayed three times. In other words, the picture for three fields will be displayed. In FIG. 4, the arrow (↓) represents a picture displayed repeatedly by the repeat first field command. As described above, the 3-2 pull down has a function capable of converting the video with 24 frames/second into the video with 30 frames/second.
(5) Structure of MPEG Video Decoder (No. 2)
FIG. 5 is a block diagram exemplifying a MPEG video decoder to cope with the 3-2 pull down. This MPEG video decoder consists of a bit-stream input terminal 160, a bit-stream buffer 161, a picture decoding section 162, a decoding frame buffer 163, a decoding control section 164 and a display control section 165.
The bit-stream buffer 161 stores a bit-stream inputted from the input terminal 160, and outputs the bit-stream sequentially one picture by one picture to the picture decoding section 162. The picture decoding section 162 decodes the bit-stream sent from the bit-stream buffer 161. The picture decoded by the picture decoding section 162 is transferred to the decoding frame buffer 163.
The decoding frame buffer 163 has a memory area for, for example, three pictures, and the memory area is partitioned for each picture. Each of the memory area partitioned for one picture is called a bank. Each of the respective banks has a specific address, i.e., a bank address.
The decoding control section 164 incorporates a V-Sync generator (not shown) for generating a vertical synchronous signal (hereinafter, referred to as a V-Sync) therein. The decoding control section 164 issues a decoding start command 172 in synchronization with the V-Sync outputted from the V-Sync generator. The picture decoding section 162 starts to decode the picture in response to-the decoding start command 172. The decoding start command 172 is principally issued once for two field time, that is, once for one frame time. This is because, since the displaying speed is set to a value equivalent to a time for displaying one picture within one frame, the decoding speed must be made to be equal to the displaying speed.
When a certain quantity of the bit-stream is stored in the bit-stream buffer 161 after turning on the power source, i.e., after a cold start, the decoding control section 164 issues an initial decoding start command 171. The timing when the initial decoding start command 171 has no relation to the V-Sync.
The display control section 165 has four registers of a re-order register 165a, a current register 165b, a field delay register 165c and a display register 165c. In addition, the decoding start command 172, the V-Sync 175 and the bank address 176 are inputted from the decoding control section 164 to the display control section 165, and various kinds of parameters 173 such as a sequence parameter and a picture parameter which were obtained by decoding the bit-stream are inputted to the display control section 165 from the picture decoding section 162. It should be noted that the bank address 176 is data indicating which bank of the decoding frame buffer 163 the decoded picture is stored. The display control section 165 outputs a field wait command 174 to the decoding control section 164 when later-described conditions are satisfied. The field wait command 174 is the one for allowing the display control section 165 to wait the issue of the decoding start command 172 for a period of one frame.
Furthermore, the display control section 165 issues a display starting command 178 after later described conditions are satisfied. The display starting command 178 issued from the display control section 165 permits a specified picture to be transferred to the display unit from the decoding frame buffer 163, and a picture is displayed on the display unit.
The four registers 165a to 165d of the display control section 165 will be described with reference to the schematic view of FIG. 6 below.
{circle around (1)} Re-Order Register 165a 
The re-order register 165a stores the parameter of the I and P pictures and the bank address thereof. The I and P pictures are not displayed immediately after completion of decoding them, a rearrangement for replacing the I and P pictures with the B picture (re-ordering) must be executed. In order to execute the rearrangement, the parameter and bank address of the I and P pictures are once shunted to the re-order register 165a. 
{circle around (2)} Current Register 165b 
The current register 165b stores the parameter and bank address of the picture to be displayed. Since the B picture is displayed immediately after completion of decoding the B picture, the parameter and bank address of the B picture are not stored in the re-order register 165a, but stored in the current register 165b. 
The display control section 165 analyzes the parameter stored in the current register 165b, and if a repeat first field flag is “1”, the display control section 16 issues the field wait command 174 to the decoding control section 164.
{circle around (3)} Field Delay Register 165c 
In order to make the decoding time equal to one frame time The field delay register 165c allows the bank address transferred from the current register 165c to be delayed by a period for one field, and then transfers the bank address to the display register 165d in the subsequent stage. If the field delay register 165c were not present, a field slot at the display timing becomes identical to the field slot immediately after the field slot at the decoding timing, resulting in a displaying at an incorrect timing. Data stored in the field delay register 165c is only the bank address 176.
{circle around (4)} Display Register 165d 
The display register 165d stores the bank address of the picture that is being displayed. In other words, the display control section 165 issues the display starting command so as to display the picture indicated by the bank address which is stored in the display register 165d. Data stored in the display register 165d is only the bank address 176.
As shown in FIG. 6, these four registers 165a to 165d form a shift register construction. Shift pulses from the re-order register 165a and the current register 165 are the decoding start command 172, and shift pulses from the filed delay register 165c and the display register 165d are the V-Sync 175. While the bank address 176 shifts from the re-order register 165a to the display register 165d thoroughly, the parameter 173 shifts merely from the re-order register 165a to the current register 165b. 
Next, an operation of the above-described MPEG video decoder will be described with reference to the timing charts of FIGS. 7 and 8. It should be noted that in this example, the bit-stream shall be inputted in the order of the I picture I2, the B picture B0, the B picture B1, the P picture P5, the B picture B3, the B picture B4 . . . , and the bit-stream shall be displayed in the order of the picture B0, the picture B1, the picture I2, the picture B3, the picture B4, the picture P5, . . . Moreover, it should be also noted that the repeat first field command shall be added to the B pictures B0 and B4 and the I picture I2.
The MPEG bit-stream sent from the transmission path or the storage media is first stored in the bit-stream buffer 161. When a certain quantity of data, i.e., data for one picture, is stored in the bit-stream buffer 161, the decoding control section 164 issues the initial decoding start command 171. Upon receipt of the initial decoding start command 171, the picture decoding section 162 decodes only the picture header (I2) of the initial picture I2, and upon completion of decoding the picture header (I2), the picture decoding section 162 stops the decoding processing (time t0).
Thereafter, the decoding control section 164 issues the decoding start command 172 at the timing in synchronization with the V-Sync (time t1). Upon receipt of the decoding start command 172, the picture decoding section 162 start to decode the coefficient other than the picture header of the picture I2 (hereinafter, referred to simply as coefficient). When decoding for the coefficient of the picture I2 is completed, the picture decoding section 162 subsequently decodes the picture header (B0) of the subsequent picture B0. Upon completion of decoding the picture header (B0) of the picture B0, the picture decoding section 162 stops the decoding processing (time t2).
On the other hand, the display control section 165 receives the parameter of the picture I2 from the picture decoding section 164 at the time t1, and stores the parameter in the re-order register 165a thereof. At this time, re-order register 165a stores the parameter of the picture I2 at the timing in synchronization with the decoding start command 172, by the use of the decoding start command 172 as a latch pulse.
At the time t3, the decoding control section 164 issues the decoding start command 172 in synchronization with the V-Sync 175 again, so that decoding of the coefficient of the picture B0 is started by the picture decoding section 162. At the same time, the parameter 173 of the picture B0 is stored in the current register 165b. 
When the parameter of the picture B0 is stored in the current register 165b at the time t3, the display control section 165 analyzes the parameter that has been stored in the current register 165b. As a result, since the repeat first field flag of the picture B0 is “1”, the display control section 165 issues the field wait command 174 to the decoding control section 164 (time 3.5).
Upon receipt of the field wait command 174, the decoding control section 164 delays the issue of the decoding start command 172 for the picture B1, which was to be issued at the time t5, by a period for one field, and issues the decoding start command 172 at the time t6.
When the decoding control section 164 issues the decoding start command 172 for the picture B1 at the time t6, the decoding of the coefficient of the picture B1 is started in the picture decoding section 162, and, at the same time, the parameter of the picture B1 is stored in the current register 165b of the display control section 165. The display control section 165 analyzes the parameter that has been stored in the current register 165b. Since it is found from the analysis result that the repeat first field flag of the picture B1 is “0”, the display control section 165 does not issue the field wait command 174.
Since the field wait command is not issued, the decoding control section 164 does not wait the issue of the decoding start command 172 for the subsequent picture P5 by a period of one field, and issues the decoding start command 172 at the time t7.
When the decoding start command 172 for the picture P5 is issued at the time t7, the parameter of the picture I2 that has been stored in the re-order register 165a up to the time t7 is shifted to the current register 165b, and the parameter of the picture P5 is stored in the reorder register 165a. 
As a result of the analysis for the parameter stored in the current register 165b by the display control section 165, since the repeat first field flag of the picture I2 is “1”, the display control section 165 issues the field wait command 174.
These operations are repeated from this point, in other words, if the repeat first field flag of the picture to be subsequently displayed is “1” as a result of the investigation for the current register 165b, the display control section 165 issues the field wait command 174, and the decoding control section 164 delays the issue of the decoding start command 172 for a period of one field. By repeating these sequential operations, the 3-2 pull down is realized. To be specific, the conventional MPEG video decoder executes the 3-2 pull down by successfully adopting a method to suspend the decoding for a period of one frame in response to the repeat first field command.
The inventor of this application thinks that the above-described MPEG video decoder involves the following problems. Specifically, if a data rate is substantially constant like a CBR coding, a time required for decoding the bit-stream for one picture will be substantially even, so that decoding the bit-stream for one picture within the one frame time is comparatively easy. However, in the case where a VBR coded bit-stream is decoded like in terminal devices of ATMs and DVD players, the data rate greatly varies, so that the bit-stream for one picture cannot be often decoded within one frame time. When the bit-stream for one picture cannot be decoded within one frame time, decoding of the bit-stream is completed by using a time for a subsequent one frame. Then, the picture data for one frame, which is to be outputted to the display unit, is thinned out, so as to control the play back time. An operation to control the play back time by thinning out the picture data as described above is called an error-concealment.
When the VBR coded bit-streams of the terminal devices of the ATMs, the DVD players and the like are decoded, a time more than one frame time is often taken for decoding the bit-stream for one picture because of variations of the data rate as described above, so that the error concealment must be frequently carried out, resulting in difficulty of a smooth moving picture play back.
Moreover, when the above-described conventional MPEG video decoder tries to realize the 3-2 pull down and slow play backs at a ½ time speed and a ¼ time speed simultaneously, a disadvantage occurs. This is because the conventional MPEG video decoder realizes the 3-2 pull down by a method to suspend the decoding for one frame time, and the slow play back is realized also by the same method. The foregoing disadvantage will be described in more detail with reference to the timing charts of FIGS. 9 and 10.
It is assumed that a ½ time speed display command (hereinafter, referred to as a ½ slow play back command) be issued at the time t2.2. In the conventional MPEG video decoder, the ½ slow play back command is inputted to the decoding control section 164. The decoding control section 164 samples the ½ slow play back command at the timing of the decoding start command 172 issued by the decoding control section 164 itself, so as to perform the decoding control (time t3). To be specific, the decoding control section 164 performs the decoding control in such manner that if the ½ slow play back command is “1” at the time when the decoding start command 172 is issued, the decoding of the subsequent picture is started after delaying by one frame time, and the picture for which the decoding has just started is displayed for two frame time.
Since one picture is displayed only for one frame time in the ordinary play back, the displaying of one picture for a period of two frame time implies that the video is displayed at a speed of one-half that of the ordinary play back.
In this example, the result. Obtained by sampling the ½ slow play back command at the time t3 is “1”. Accordingly, after the decoding for the picture B0 is finished, the decoding for the subsequent picture B1 is delayed by one frame time, and the decoding for the picture B1 is begun at the time t6.5.
Hereupon, because the picture B0 exhibits the repeat first field flag of “1”, the field wait command 174 is issued from the display control section 165 (time 3.5). Accordingly, the decoding control section 164 executes both “wait the decoding for one frame time (two field time)” in response to the ½ play back command and “wait the decoding for one field time” in response to the field wait command 174. In this case, since the wait time in the latter is shorter than that of the former, the latter is neglected (time t5 to t6). Namely, although the conventional MPEG video decoder is originally obliged to execute “3-2 pull down displaying and ½ slow play back”, the conventional MPEG video decoder merely execute “½ slow play back”.
As shown in FIGS. 9 and 10, when it is assumed that the ½ slow play back command be “1” from the time t2.2 to t6.7, though the picture B0 must be originally displayed for a period of the six frames, the picture B0 is displayed only for a period of two frames.
The object of the present invention is to provide a MPEG video decoder, in which the necessity of an error concealment hardly occurs even in the case of decoding a MPEG bit-stream that has been subjected to a VBR, enabling a smooth moving picture play back.
Another object of the present invention is to provide a MPEG video decoder which is capable of displaying a video by a 3-2 pull down as well as by a slow play back, and a method for decoding a MPEG video.